1. Field of the Invention
The present invention relates to an ESD protection device, and more particularly, to a technique using a silicon controlled rectifier (SCR) in a rail based non-breakdown (RBNB) ESD protection device that protects a micro chip from ESD stress.
2. Background of the Related Art
Semiconductor integrated circuits are very sensitively affected by high voltage flowing into from electrostatic discharge (or static electricity) generated outside. If the high voltage abruptly flows into a chip due to such electrostatic discharge (ESD), the flowing in high voltage destroys thin insulators, channels, and the like formed in the integrated circuit and destroys the chip itself.
An ESD protection apparatus previously discharges high voltage or high current momentarily flowing into the integrated circuit so that the high voltage or current cannot flow into other circuits in the chip.
A semiconductor (or silicon) controlled rectifier (SCR) using a PN junction is widely used as the ESD protection apparatus.
Since the SCR discharges a large amount of current per unit area, the SCR is spotlighted as an ESD protection apparatus in early stage integrated circuits. However, as the integrated circuits are integrated in further higher density and the size of a chip is reduced, due to high turn-on voltage (trigger voltage or threshold voltage) of the SCR and low holding voltage that maintains the turn-on state of the SCR, the SCR is difficult to be applied to recent integrated circuits.
On the other hand, a method of protecting internal core circuits (or input and output buffers) from ESD stress in each input/output (I/O) pad can be classified into a direct pad based ESD (DPBESD) protection circuit and a PowerRail based ESD (PRBESD) protection circuit.
FIG. 1 is a circuit diagram showing a general DPBESD protection circuit, in which an ESD protection circuit in each input/output pad copes with ESD stress flowing into the I/O pad.
Although the DPBESD protection circuit does not need to consider parasitic bus resistance between each I/O pad and power clamp at all and can implement the best ESD protection performance if the ability of handling stress current of an ESD protection circuit applied to each I/O pad is favorable, it is difficult to expect an stable and efficient ESD protection performance if a favorable ESD protection circuit cannot be implemented for a given technology.
In addition, since a separate ESD protection circuit should be installed in each I/O pad, there is a problem in that efficiency of layout area is lowered, and in the worst case, it is impossible to secure a layout area for installing a separate ESD protection circuit in each I/O pad.
FIG. 2 is a circuit diagram showing operational characteristics of a general PRBESD protection circuit, which is a method of handling ESD stress by installing only a bypass diode path in each I/O pad and using a power clamp installed between power rings that are between power voltage Vdd and ground voltage Vss.
Since the PRBESD protection circuit does not have an ESD protection circuit one-to-one corresponding to each I/O pad, it is relatively further difficult to implement a stable ESD protection characteristic compared with a DPBESD protection circuit. However, it is advantageous in that since a separate ESD protection circuit does not need to be installed for each I/O pad, efficiency of a layout area is high.
In addition, in handling the ESD stress, it is possible to be assisted with current of a vertical PNP BJT of a CMOS device and N-well of the entire chip.
Contrarily, when parasitic bus resistance (including resistance of forward operation diode path) between each I/O pad and the power clamp is too high, a problem may occur since stress current flows into the core circuit (or output and input buffers) before the ESD protection power clamp operates.
A non-breakdown type (NB type) power clamp is employed in the PRBESD protection circuit as a device for particularly processing ESD stress current, which is named as a rail based non-breakdown (RBNB) ESD protection circuit.
Such an RBNB ESD protection circuit generally employs a method of configuring an active clamp using normal operation of a big MOS transistor.
Accordingly, a triggering circuit is needed for the power clamp MOS transistor, and it is advantageous in that the risk of damaging the core circuit (or input and out buffers) is low since triggering voltage of the power clamp MOS transistor is low in a situation of ESD stress.
FIG. 3 is a view showing the configuration and operation principle of a so-called “1RC3Inv_Std” ESD protection circuit, which is a kind of generally used RBNB (Rail Based Non-Breakdown) ESD protection scheme.
As shown in FIG. 3, the “1RC3Inv_Std” ESD protection circuit includes a rising time detector 10 for detecting a rising time of voltage applied between Vdd-Vss lines, a pre-driver 20 for driving and outputting output of the rising time detector 10, and a power clamp 30 operating according to a signal driven by the pre-driver 20 and controlling flow of current between the Vdd-Vss lines.
The rising time detector 10 comprises one RC-filter where a resistor R1 and a capacitor C1 are connected between the Vdd-Vss lines in a series and an inverter INV1 for inverting and outputting electric potential of node N0 between the resistor R1 and the capacitor C1.
The pre-driver 20 comprises two inverters Inv2 and Inv3 connected in a series in the form of a chain in order to buffer and output the output of the rising time detector 10.
The power clamp 30 comprises a big MOS transistor (BigMN) that operates using output voltage outputted from the pre-driver 20 as gate input.
Since such an RBNB ESD protection circuit uses saturation current (drain current) (Idsat current) of a normal MOS transistor, it is disadvantageous in that efficiency of a layout area is low since a large active width is needed.
As a technique for improving the disadvantage of low layout area efficiency of the RBNB ESD protection circuit using a big MOS transistor (BigNM) of the prior art, it is proposed a technique using an SCR having a superior current driving characteristic in comparison with an area, instead of the big MOS transistor (BigNM), as shown in FIG. 4.
Referring to FIG. 4, it is a configuration circuit diagram of a so-called “1RC1Inv_SCR” ESD protection circuit, which is one of RBNB ESD protection schemes, comprising a rising time detector 40, a pre-driver 50, and a power clamp 30.
Here, the power clamp 60 includes an SCR operating according to a signal driven by the pre-driver 50 and controlling flow of current between the Vdd-Vss lines.
The rising time detector 40 includes one RC-filter where a resistor R1 and a capacitor C1 are connected between the Vdd-Vss lines in a series.
The pre-driver 20 includes an inverter INV1 having an NMOS transistor NM and a PMOS transistor PM for inverting and outputting electric potential of node N0 of the rising time detector 40, which applies a bias to the N-well of the SCR power clamp 60 and turns on and off the SCR when the circuit is in a normal operation or applied with ESD stress.
According to such a configuration, when difference of voltage between Vdd-Vss changes in a function of time, since voltage of N0 follows the difference of voltage between Vdd-Vss with an RC delay due to the RC-filter, the “1RC1Inv_SCR” ESD protection circuit operates as described below in situations of ESD stress, normal power ramp up, and normal power on.
First, in the ESD stress situation, if ESD stress having a normal rising time (<<R1C1) and interval (≦R1C1) is applied between the Vdd-Vss lines while power is not applied between the Vdd-Vss lines, i.e., when Vdd=0 and Vss=0, N0 is in a low state, PM1 is in an on state, N1 is in a high state, and SCR is in an on state during the rising time and interval of the ESD stress.
That is, the SCR is triggered by the inverter Inv1 to operate and thus copes with the ESD stress current.
In the case of the normal power ramp-up situation, if power ramped up at a speed lower than a time constant R1C1 of the RC filter is applied to Vdd-Vss while power is not applied between the Vdd-Vss lines, i.e., when Vdd=0 and Vss=0, the state of N0 is low, PM1 is on, and N1 is high is maintained in the initial stage of the ramp-up. Therefore, a bias is applied to the N-well of the SCR, and the SCR is in a situation difficult to be turned on and thus maintains the off state.
In the case of the normal power on situation, when normal power is applied between the Vdd-Vss lines, i.e., when Vdd=3.3V and Vss=0V, basically, the state of N0 is low, PM1 is on, N1 is high, and the SCR is off is maintained, and thus current does not flow through the SCR.
As a result, in the “1RC1Inv_SCR” ESD protection circuit, the ESD stress current is coped with since the SCR operates in the ESD stress situation, and leakage current is not induced between the Vdd-Vss power lines since the SCR doe not operate in the normal operation situation.
However, since an inverter having low current drive capability of low degree of integration is used in this technique in order to trigger the SCR, it is disadvantageous in that efficiency of the layout area is low.